1. Field of the Invention
The present invention relates generally to the field of memory management and, more specifically, to supporting late DRAM bank hits.
2. Description of the Related Art
One element of a memory subsystem within certain processing units is a Level 2 Cache memory (referred to herein as “L2 cache”). The L2 cache is a large on-chip memory that temporarily stores data being used by the various clients. This data may be retrieved from or written to an external memory (referred to herein as “DRAM”). A memory controller (referred to herein as “DRAM controller”) manages the flow of data being transmitted to or retrieved from the DRAM.
A DRAM typically includes multiple DRAM banks, where each bank is divided into multiple bank pages. A bank page within a DRAM bank needs to be activated before data can be transmitted to or retrieved from that bank page. Only one bank page within a specific DRAM bank can be active at any given clock cycle. After the last data transmission to or data retrieval from a particular bank page is complete, a pre-charge command is transmitted to the DRAM bank, causing the bank page to be closed. Future data transmissions and data retrievals associated with that bank page require the re-activation of that particular bank page. As is well-known, activating and pre-charging bank pages within a DRAM bank are both extremely time consuming operations. Therefore, if either of these two operations is executed too frequently, the overall system performance may be severely impacted.
Conventional DRAM controllers wait a pre-determined number of clock cycles after the last read or write command has been processed by a particular bank page before transmitting a pre-charge command to the DRAM bank. The DRAM controllers implementing this scheme wait the pre-determined number of clock cycles to allow potential read and write commands that are associated with that bank page to be processed. This scheme often times forces a bank page to remain activated even when no new read or write commands are transmitted increasing, increasing the latency of the overall system
Further, the DRAM controller transmits a separate command for each activate and pre-charge operation to the DRAM bank through a command bus. The same command bus is used to transmit read and write commands to the DRAM bank. Transmitting a command for each activate and pre-charge operation uses up the limited bandwidth on the command bus that may be used to transmit read and write commands, thereby causing command bus bandwidth inefficiencies.
As the foregoing illustrates, what is needed in the art is a more efficient mechanism for determining when to activate and pre-charge the different bank pages within a DRAM bank.